GATEComputer Organization & Architecture
Computer Organization & Architecture for GATE
~7 marks — memory hierarchy is usually the largest single contributor.
📊 ~5 Q · ~7 marks (7% of the paper)🖥️
How toppers play this section
This subject is almost entirely numerical, and the numericals fall into three families that recur every year: pipelining speedup with hazards, cache hit-rate and average access time, and effective address computation under a named addressing mode. Memory hierarchy alone usually contributes the most marks, and its questions turn on splitting an address into tag, index and offset fields correctly — get that split wrong and every subsequent number is wrong. Pipelining questions are decided by identifying which overlap is unsafe rather than by the speedup formula itself. The I/O chapter is smaller but reliably examined through the interrupt-versus-DMA comparison, which is really a question about who waits and who moves the bytes.
Chapters
Built to the GATE blueprint — notes, shortcuts, solved PYQ-style examples and practice in every chapter.
Topic-wise weightage in GATE
Expected question counts from previous-year paper analyses. Topics with an arrow already have a full chapter.
| Topic | GATE CS — single 3-hour CBT paper Q | Score used for M.Tech admission / PSU recruitment Q | Priority |
|---|---|---|---|
| Machine Instructions & Addressing Modes | ~1 | Medium | |
| ALU, Data-path & Control Unit | ~1 | Medium | |
| Instruction Pipelining & Hazards | ~2 | Very high | |
| Memory Hierarchy: Cache & Main Memory | ~2-3 | Very high | |
| I/O Interface: Interrupt & DMA Mode | ~1 | Medium |
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